To tolerate faults such as a single event upsets (SEUs) or single event transients (SETs), typical field programmable gate arrays (FPGAs) provide either fixed redundant circuitry or no redundancy at all, forcing users to program any required redundancy in firmware and increasing overhead costs. Although hardware redundancy provides high performance and assurance, many applications need to be only partially protected from SEUs/SETs, while other parts of the applications require higher capacity.
Users can now make the choice based on their requirements.
NASA’s Johnson Space Center has designed a technology that enables selective reconfiguration of FPGAs and similar devices between redundant and non-redundant operation. This allows users to create the right mix of reliability and high capacity to meet application needs. This innovation allows the flexibility of firmware redundancy while maintaining the efficiency and simplicity of hardware-based redundancy.
- Improved performance: Hardware redundancy saves at least one “logic level” over firmware, increasing design speed and reducing power consumption.
- Increased capacity: User can choose triple-redundancy in only the needed areas.
- Lower manufacturing cost for end users: Eliminating unnecessary redundancy may enable user designs to fit into smaller devices.
- Lower development cost for end users: Eliminating the design of firmware redundancy reduces design time.
This technology is particularly beneficial in the high-radiation environments found in the aerospace industry and is currently available for licensing from NASA’s Johnson Space Center.
For more information, contact: Fuentek, LLC (919) 249-0327 firstname.lastname@example.org